On my option to this yr’s Hackaday SuperConference I noticed an article on EE Instances about somebody taking the $22 Lattice iCEstick and turning it right into a logic analyzer full with a Python app to show the waveforms. This jumped out as fairly cool to me provided that there actually isn’t a ton of RAM on the stick, mainly none that isn’t contained within the FPGA itself.
[Jenny List] has additionally written concerning the this software as created by [Kevin Hubbard] of Black Mesa Labs and [Al Williams] has an excellent set of posts about utilizing this similar $22 analysis board doing floor up Verilog design utilizing open supply instruments. Even in the event you don’t find yourself utilizing the stick as a logic analyzer over the lengthy haul, it’ll be very straightforward to seek out many different tasks the place you may recompile to invent a brand new function for it.
In regards to the Stick
The Lattice iCEstick is a small FPGA analysis PCB with solely a little bit little bit of help circuitry; mainly simply the FPGA, a clock, some SPI flash reminiscence and a USB interface. There are additionally some connectors and pin pads in addition to an IR transceiver to get alerts on and off the meeting.
The FPGA itself is an iCE40HX1K with 160 logic blocks in it and as much as eight kilobytes of RAM, to me this feels like a medium-small machine, nevertheless since FPGA architectures differ I actually can’t say for certain except I wetre to load a few older designs I’ve used up to now for comparability.
I had been the unique SUMP.org analyzer for dropping onto one among my little customized FPGA boards I make when I’m bored. I consider the logic analyzer software as a RAM pump (round buffer controller) with a UART on one facet and many I/O strains on the opposite. Basically the period of time desired to be captured at any specific clock frequency, interprets on to the quantity of RAM wanted. Defending the FPGA from the tough realities and in some circumstances the working voltages current within the goal system, can be essential if utilizing it for severe work.
[Kevin] refers to his design as SUMP2 and for good purpose as there may be some departure from the unique SUMP structure. The SUMP2 makes use of a easy lossless compression scheme referred to as Run Size Encoding (RLE) the place as a substitute of sending a lot of zero’s or 1’s in a row, it sends a bit worth and what number of instances to repeat that worth earlier than the following transition to a special bit state. The SUMP2 design compresses the info not only for sending it to the controlling pc but additionally earlier than storing it within the restricted quantity of RAM within the iCE40. Once more which means it isn’t essentially the period of time (or variety of pattern clocks) that determines how a lot knowledge is saved however as a substitute the variety of transitions recorded.
Trying on the block diagram it may be seen that the structure additionally helps non-RLE encoded knowledge sampling as denoted by the alerts named “dwords” on the backside left.
To get extra of a hands-on expertise I like to recommend downloading the complete undertaking after which obtain the free FPGA design software program iCEcube2 from Lattice, although they do require that the consumer submit the MAC handle of their pc to acquire the license key to run the software program.
Within the video I step by means of loading the undertaking and all for the steps as much as compiling the RTL code and programming the FPGA. That’s my method of claiming I’m not going to repeat all the steps right here.
The opposite piece is the Python GUI which consists of two modules, a server module named bd_server.py which camps on a TCP port and interfaces to the USB, and the core sump.py module which runs as a pygame software. Earlier than operating the app a few modules should be loaded (that is all contained within the set up directions), specifically pyserial, and pygame. I used the next instructions (I’m not a Python particular person, you could have a extra insightful or environment friendly l method):
“python -m pip set up -U pip setuptools” “python -m pip set up -U pip pyserial” “python -m pip set up -U pip wheel” “python -m pip set up -U pip Pygame”
However wait, nothing is kind of that straightforward, the directions (and the video) stroll the consumer by means of additionally setting VCP on the USB B port of the Lattice machine driver. When and in case you are profitable you can be rewarded with the worth for the digital COM port.
The following factor to do is to run the bd_server app from the Home windows CMD immediate “begin bd_server.py”. It could fail the primary time nevertheless it leaves behind a configuration file “bd_server.ini” through which the settings for the COM port and will be edited. Altering “AUTO” to the right COM port seems to be a typical requirement. Operating the app a second time resulted in a “5 by 5” message indicating that it was correctly operating.
From right here one is free to start out analyzing and modifying if y’all have an curiosity to take action. For me, I discovered a line in sump.py and un-commented it in order that the menu supplied a direct option to make issues greater so my previous eyes might truly see what I used to be (seems “residence” and “finish” all the time work for increasing the road peak however I solely know that from studying the code.
One notice is that the FPGA used right here is barely three.3V tolerant, [Kevin] has a public area PCB up at OSHPark for changing to 5V.
When you have a severe want for a logic analyzer, use a severe analyzer, nevertheless if you wish to spend a minimal sum of money and/or like open supply stuff, test this out.